Internal Asset Exposed to Unsafe Debug Access Level or State

Description

Demonstrations

The following examples help to illustrate the nature of this weakness and describe methods or techniques which can be used to mitigate the risk.

Note that the examples here are by no means exhaustive and any given weakness may have many subtle varieties, each of which may require different detection methods or runtime controls.

Example One

The JTAG interface is used to perform debugging and provide CPU core access for developers. JTAG-access protection is implemented as part of the JTAG_SHIELD bit in the hw_digctl_ctrl register. This register has no default value at power up and is set only after the system boots from ROM and control is transferred to the user software.

1 bit0x0 = JTAG debugger is enabled (default)JTAG_SHIELD0x1 = JTAG debugger is disabled

This means that since the end user has access to JTAG at system reset and during ROM code execution before control is transferred to user software, a JTAG user can modify the boot flow and subsequently disclose all CPU information, including data-encryption keys.

The default value of this register bit should be set to 1 to prevent the JTAG from being enabled at system reset.

Example Two

The example code below is taken from the CVA6 processor core of the HACK@DAC'21 buggy OpenPiton SoC. Debug access allows users to access internal hardware registers that are otherwise not exposed for user access or restricted access through access control protocols. Hence, requests to enter debug mode are checked and authorized only if the processor has sufficient privileges. In addition, debug accesses are also locked behind password checkers. Thus, the processor enters debug mode only when the privilege level requirement is met, and the correct debug password is provided.

The following code [REF-1377] illustrates an instance of a vulnerable implementation of debug mode. The core correctly checks if the debug requests have sufficient privileges and enables the debug_mode_d and debug_mode_q signals. It also correctly checks for debug password and enables umode_i signal.

module csr_regfile #(
...

  // check that we actually want to enter debug depending on the privilege level we are currently in
  unique case (priv_lvl_o)

    riscv::PRIV_LVL_M: begin

      debug_mode_d = dcsr_q.ebreakm;



...


    riscv::PRIV_LVL_U: begin

      debug_mode_d = dcsr_q.ebreaku;



...

  assign priv_lvl_o = (debug_mode_q || umode_i) ?  riscv::PRIV_LVL_M : priv_lvl_q;

...

  debug_mode_q  <= debug_mode_d;

...

However, it grants debug access and changes the privilege level, priv_lvl_o, even when one of the two checks is satisfied and the other is not. Because of this, debug access can be granted by simply requesting with sufficient privileges (i.e., debug_mode_q is enabled) and failing the password check (i.e., umode_i is disabled). This allows an attacker to bypass the debug password checking and gain debug access to the core, compromising the security of the processor.

A fix to this issue is to only change the privilege level of the processor when both checks are satisfied, i.e., the request has enough privileges (i.e., debug_mode_q is enabled) and the password checking is successful (i.e., umode_i is enabled) [REF-1378].

module csr_regfile #(
...

  // check that we actually want to enter debug depending on the privilege level we are currently in
  unique case (priv_lvl_o)

    riscv::PRIV_LVL_M: begin

      debug_mode_d = dcsr_q.ebreakm;



...


    riscv::PRIV_LVL_U: begin

      debug_mode_d = dcsr_q.ebreaku;



...

  assign priv_lvl_o =  (debug_mode_q && umode_i) ? riscv::PRIV_LVL_M : priv_lvl_q;

...

  debug_mode_q  <= debug_mode_d;

...

See Also